module shiftreg # (parameter N=4)(shift, load, in, sin,clk,sout,q, reset);
    input [N-1:0] in;
    input shift;
    input load;
    input sin;
    input clk;
    input reset;
    output sout;
    output reg [N-1:0] q;
    always @ (posedge clk or posedge reset)
    begin
        if (reset) q <= 0;
        else if (load&~shift)
        begin
            q <= in;
        end
        else if(shift&~load)
        begin
            q <= {sin, q[N-1:1]};
            
        end
        else if (shift & load)
        begin
            q <= {sin, in[N-1:1]};
        end
    end
    assign sout = load ? in[0] : q[0];
endmodule

module shiftregC(shift, load, in, sin,clk,sout,q, reset);
    input in;
    input shift;
    input load;
    input sin;
    input clk;
    input reset;
    output sout;
    output reg q;
    always @ (posedge clk or posedge reset)
    begin
        if (reset) q <= 0;
        else if (load&~shift)
        begin
            q <= in;
        end
        else if(shift)
        begin
				q <= sin;
        end
    end
    assign sout = load ? in : q;
endmodule
